Sense amplifier role
In DRAM, sense amplifiers detect the tiny voltage change on bitlines and amplify it to readable logic levels (0 or 1).
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| Term | Definition |
|---|---|
Sense amplifier role | In DRAM, sense amplifiers detect the tiny voltage change on bitlines and amplify it to readable logic levels (0 or 1). |
Precharge phase | Step in DRAM where bitlines are reset to a neutral voltage before accessing a new row. |
Activate command | Tells DRAM to open a specific row by connecting it to the sense amplifiers via the wordline. |
Read command | Tells DRAM to output the data from the activated row to the memory bus. |
Write command | Tells DRAM to store new data into the currently activated row. |
Row buffer | Temporary storage inside a DRAM bank that holds data from the last activated row. |
Bank | Independent section of a DRAM chip that can operate in parallel with others for higher performance. |
Bank interleaving | Technique of accessing multiple banks alternately to improve throughput and hide latency. |
tRCD (Row to Column Delay) | Time delay between activating a row and accessing a column within that row. |
tRP (Row Precharge Time) | Time required to close a currently open row before opening another. |
tRAS (Row Active Time) | Minimum time a row must remain open for reliable data operations. |
CAS latency (CL) | Number of clock cycles between sending a READ command and receiving the data. |
Command queue | In memory controllers, the list of pending read/write operations waiting to be executed. |
Memory scheduling | Order in which the memory controller issues commands to optimize performance and reduce conflicts. |
Dual-channel memory | Configuration where two memory channels operate simultaneously for doubled bandwidth. |
Quad-channel memory | Configuration using four channels for even greater bandwidth. |
Memory timing example | Example: DDR5-6000 CL30 means 6000 MT/s speed and 30 cycles CAS latency. |
Burst length | Number of consecutive data words transferred per memory access. |
Prefetch | Mechanism that fetches more data than immediately needed to improve efficiency. |
Refresh interval | Typical DRAM cells must be refreshed every ~64 milliseconds to retain data. |
Auto-refresh | Automatic process where the memory controller refreshes DRAM rows periodically. |
Retention time | How long a DRAM cell can hold charge before data begins to degrade. |
Why DRAM needs refreshing | Because capacitors leak charge over time, even if power is maintained. |
Power-down mode | Low-power state of DRAM to save energy when idle. |
Self-refresh mode | Mode where DRAM refreshes itself internally without CPU involvement. |
On-die ECC (Error Correction Code) | Feature in modern DDR5 that corrects small errors inside the chip before data leaves it. |
External ECC | Used in servers to detect and correct multi-bit memory errors for high reliability. |
Row hammer effect | Phenomenon where repeatedly accessing one row causes electrical interference in adjacent rows, flipping bits. |
Row hammer mitigation | DRAM manufacturers add refresh logic or error correction to prevent this effect. |
Burst transfer | How DRAM sends multiple consecutive data words per request to increase efficiency. |
Address mapping | Translation of CPU addresses into DRAM row, column, bank, and channel addresses. |
Subarray | Smaller section within a DRAM bank that improves internal parallelism. |
Rank interleaving | Alternating between ranks to improve memory throughput. |
DRAM scaling challenge | As transistors and capacitors shrink, it becomes harder to store enough charge and prevent leakage. |
Why DRAM is expensive | Requires precise manufacturing and high density of small capacitors. |
Why SSDs are cheaper per GB | Use NAND flash which packs more bits per cell and is non-volatile. |
LPDDR (Low Power DDR) | Mobile DRAM designed for phones and laptops; optimized for lower power use. |
GDDR (Graphics DDR) | High-bandwidth DRAM type used in GPUs for intensive data throughput. |
HBM (High Bandwidth Memory) | Stacked DRAM connected to GPU/CPU with very wide bus for massive bandwidth. |
Memory hierarchy example | CPU cache (nanoseconds) → DRAM (tens of ns) → SSD (microseconds) → HDD (milliseconds). |
CPU–DRAM communication | The CPU requests data via the memory controller over high-speed buses. |
NUMA (Non-Uniform Memory Access) | In multi-CPU systems, memory is divided so each CPU has faster access to its local memory. |
Memory bottleneck | The situation where CPU performance is limited by slower memory access. |
Future of DRAM | Research exploring new materials and 3D structures to increase density and reduce energy. |