DRAM
Volatile memory used by computers to store data that the CPU needs quickly; data is lost when power is turned off.
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| Term | Definition |
|---|---|
DRAM | Volatile memory used by computers to store data that the CPU needs quickly; data is lost when power is turned off. |
SSD | Non-volatile storage device that keeps data even when power is off; slower than DRAM but much larger in capacity. |
Volatile memory | Memory that loses all stored data when power is removed. |
Non-volatile memory | Memory that retains data even without power (e.g., SSD, HDD, Flash). |
DRAM cell | A tiny circuit made of a capacitor and a transistor used to store 1 bit of data. |
Capacitor in DRAM | Stores an electric charge representing a 1 or 0. |
Transistor in DRAM | Controls whether the capacitor can be read or written to. |
Bit | The smallest unit of data, representing either a 1 or 0. |
Byte | 8 bits combined together. |
Memory array | A grid of DRAM cells organized in rows and columns. |
Wordline | The horizontal line in a DRAM array used to select an entire row of cells. |
Bitline | The vertical line in a DRAM array that carries data from the selected cells. |
Sense amplifier | Circuit that detects and amplifies the small charge difference when reading a bit from DRAM. |
Refresh cycle | Periodic recharging of DRAM capacitors to prevent data loss. |
Row access time | Time it takes to access a specific row in DRAM. |
Column access time | Time it takes to access a specific column once a row is open. |
Row hit | When a requested data is in the same row as the previous access, making retrieval faster. |
Row miss | When a new row must be opened before data can be read, causing delay. |
Latency | The delay between requesting and receiving data from memory. |
Memory bandwidth | The rate at which data can be transferred between memory and CPU. |
DIMM (Dual Inline Memory Module) | A physical board that holds multiple DRAM chips, installed on the motherboard. |
Memory controller | Coordinates communication between CPU and memory modules. |
DDR (Double Data Rate) | Technology that transfers data twice per clock cycle. |
DDR4 | Previous generation of DRAM; lower speed and efficiency than DDR5. |
DDR5 | Modern generation of DRAM; higher bandwidth and energy efficiency. |
Channel | An independent communication path between the CPU and DRAM. |
Rank | A set of DRAM chips that share the same data bus. |
SSD vs DRAM | SSD stores data permanently but is slower; DRAM is fast but temporary. |
NAND flash | Memory type used in SSDs to store data in floating-gate transistors. |
Wear leveling | SSD technique that spreads writes evenly to extend lifespan. |
Controller (SSD) | Manages data placement, error correction, and wear leveling inside SSDs. |
DRAM cache in SSD | A small DRAM buffer inside SSD that temporarily stores data to speed up operations. |
Data transfer bottleneck | Occurs when CPU waits for data from slower storage or memory. |
CPU cache | Smaller, faster memory inside the CPU to reduce access time to frequently used data. |
Memory hierarchy | Arrangement of storage types by speed and size (CPU cache → DRAM → SSD → HDD). |
Why DRAM is faster | Because it uses simple capacitor-based cells with direct electrical access. |
Why SSD is slower | Because it must access NAND cells and manage wear leveling and data mapping. |
Power loss effect on DRAM | Data is lost instantly because capacitors discharge. |
Power loss effect on SSD | Data stays safe because flash memory is non-volatile. |